Semiconductor devices within an integrated circuit chip (IC) are commonly interconnected by conductive lines, preferably made of Al, Cu and the like, their alloys or by layered metallurgy. With the increased density of the ICs, the dimensions of the interconnections have been sharply reduced. Process failures in the form of open and short-circuits have, correspondingly, become more prevalent. These problems are compounded to problems associated with high current density and electromigration, all of which have contributed in creating serious reliability concerns.
Interconnection wiring in ICs is generally fabricated using a subtractive etch method, e.g., Reactive-Ion-Etching (RIE). There are two serious drawbacks to this method, firstly, its inapplicability to copper metallurgy and, secondly, line short/open problems in an Al based metallurgy caused by the presence of a variety of defects and grain boundary attack by the etchant. Line shorts dramatically increase with decreasing pitch, limiting the pitch to approximately 0.7.mu.m. (microns) for any large scale manufacturability. Another shortcoming of the reactive ion etching relates to the high process yield loss due to conductor line opens, especially for line widths below 0.5.mu.m. Yet another shortcoming of the subtractive etch process resides in the difficulty in filling the gap between the metal lines, which in turn, raises additional reliability concerns.
The additive process that defines a fine wiring line has so far been limited to lift-off, a process well known to practitioners in the art. This process has an even wider limitation on the line width, and evidence of its use is limited to 1.0.mu.m. Another additive method, termed the `Damascene` method, has been a subject of many innovations, but has not yet gained much acceptance in manufacturing lines. Crippling factors include corrosion, metal smearing and metal impregnation into the insulator during chem-mech polishing operation. These factors have created yield problems as evidenced by the presence of, for instance, shorts between adjacent conductor lines.
An effective method of containing the problem of metal shorts in a damascene process is described in U.S. Pat. No. 5,426,330 to Joshi et al., and of common assignee. Joshi et al. teach how to effectively cap soft metal with hard metal, e.g., tungsten, to prevent smearing of soft metal during chem-mech polishing.
One of the main drawbacks of hard metal cap damascene process lies in a reduction occurring to the cross-sectional area of the high conductivity metal, causing an increase in the resistance per unit area of the conductor. A second problem is the continuous presence of deposited soft metal alongside the top edge of the trench which is exposed during the final stages of metal polishing, and which lends itself to the same perils as those described above, viz., metal smearing and resulting shorts.
The metal film discontinuity at the top edge of trenches may be achieved by evaporation techniques similar to those used for depositing soft metal. However, evaporation gives a poor trench fill in fine geometries, and hence cannot be readily extended to line widths below approximately 1 .mu.m.
Another technique that describes how to make deposited metal discontinuous at the top perimeter of a trench is disclosed in U.S. Pat. No. 3,837,907 to Berglund et al., who describe an overhang structure in a composite insulator which is constructed for the purpose of making the deposited metal discontinuous. Berglund et al. do not polish off the metal deposited on top of the insulator, but they let the conducting lines follow a parallel path to the metal deposited inside the groove. This scheme can only be used for redundant parallel lines of conductors, also the metal lines atop the insulator cannot be used for making contact to devices or vias or (via) studs below this level. Additionally, metal lines formed within the groove of such an overhang structure leaves voids along the sides and under the overhang, as illustrated in the drawings of Berglund's et al. of the aforementioned patent. In a damascene process, these voids may entrap chemicals, resulting in severe corrosion problems.
Grooves with an overhang cannot be filled by conformal coating methods, such as Chemical Vapor Deposition (CVD), because the narrow opening at the top gets laterally closed before a groove underneath is filled, thereby leaving big voids. Furthermore, no practical CVD method exists for aluminum metallurgy, and CVD of copper utilizes highly unstable precursors, barring its application in a manufacturing environment.
Recently, attention has been focused in obtaining good sidewall coverage in narrow grooves totally devoid of any overhang. One such methods is disclosed in U.S. Pat. No. 4,824,544 to Rossnagel, and of common assignee, who describes a collimated sputtering method to improve the directionality of the depositing metal atoms.
U.S. Pat. No. 5,403,779 to Joshi et al., and of common assignee, teaches a low pressure sputter deposition technique, with or without collimation, to achieve side wall coverage in narrow openings without overhang.
The aforementioned methods of Rossnagel et al. and Joshi et al. considerably improve the sidewall coverage of high aspect-ratio grooves, because the metal build-up on the top ledge of a groove (as in CVD) is curtailed by the nearly vertical direction of the depositing atoms. Not surprisingly, these methods are not applicable where lateral filling in an overhanged groove is required.
In summary, problems of leakage, short-circuits, corrosion, and the like, remain with traditional damascene methods, preventing their application to manufacturing processes.